This invention relates generally to field programmable gate arrays ("FPGAs"). Field programmable gate or logic arrays usually store configuration data to control the FPGA's configurable switches and configurable logic blocks.
A problem with prior art FPGA chips is these chips' high cost per logic gate. Another problem is the lengthy period required for calculating the routing of these configurable logic chips. One prior art FPGA chip can take hours to route by computer. Yet another problem with prior art FPGA chips is their poor gate utilization. Because of the difficulties routing prior art FPGA chips, generally only a small fraction of the gates in a prior art FPGA chip are used for a given circuit design. Another problem with prior art FPGA chips is the poor visibility of the circuits placed in these chips. It is difficult to observe the value of certain nodes of the circuit placed on a prior art FPGA chips. It is also difficult to externally set the values of certain nodes of the circuit placed on the prior art FPGA chips. This lack of visibility is especially disadvantageous if the FPGA chips are used for emulation. It is desired to have observability and controllability of many locations in a circuit being emulated and tested.
It is therefore an object of the present invention to provide an FPGA chip which is cheaper in cost per gate.
A further object of the present invention is to provide an FPGA chip which requires less computer time to route.
A still further object of the present invention is to provide an FPGA chip with a high gate utilization. It is desired that a larger percentage of the gates in the FPGA chip be used for any given circuit design.
A yet another object of the present invention is to provide an FPGA chip with better visibility and controllability.